FIFO_RX_LEVEL=not_reach, FSM_STA=idle, FIFO_FULL=not_full, CARD_BUSY=not_busy, FIFO_TX_LEVEL=not_reach, FIFO_EMPTY=not_sempty, CARD_PRESENT=not_present
Status Register
| FIFO_RX_LEVEL | FIFO RX Water Level Flag 0 (not_reach): FIFO does not reach the receive trigger level 1 (reach): FIFO reaches the receive trigger level |
| FIFO_TX_LEVEL | FIFO TX Water Level Flag 0 (not_reach): FIFO does not reach the transmit trigger level 1 (reach): FIFO reaches the transmit trigger level |
| FIFO_EMPTY | FIFO Empty 0 (not_sempty): FIFO is not empty 1 (empty): FIFO is empty |
| FIFO_FULL | sFIFO Full 0 (not_full): FIFO is not full 1 (full): FIFO is full |
| FSM_STA | Command FSM States 0 (idle): Idle 1 (sis): Send init sequence 2 (txcsb): TX CMD start bit 3 (txctb): TX CMD TX bit 4 (txcia): TX CMD index + argument 5 (txcc): TX CMD CRC7 6 (txceb): TX CMD end bit 7 (rxrsb): RX response start bit 8 (rxrir): RX response IRQ responses 9 (rxrtb): RX response TX bit 10 (rxrci): RX response CMD index 11 (rxrd): RX response data 12 (rxrc): RX response CRC7 13 (rxreb): RX response end bit 14 (cpwn): CMD path wait NCC 15 (wait): Wait; CMD-to-response turn around |
| CARD_PRESENT | Data[3] Statuss 0 (not_present): The card is not present 1 (present): The card is present |
| CARD_BUSY | Card Data Busy 0 (not_busy): Card data is not busy 1 (busy): Card data is busy |
| FSM_BUSY | Data FSM Busy |
| RESP_IDX | Response Index |
| FIFO_LEVEL | FIFO Level |
| DMA_REQ | DMA Request |